Modern integrated circuit devices continue to shrink in size as they accelerate in speed. More and more functionality is demanded of less and less device “real estate” or available circuit space, whether on the printed circuit board of an electronic appliance or on the semiconductor chip in which integrated circuits are formed.
Existing integrated circuits are essentially two-dimensional in that they are formed on the surface of flat semiconductor wafers. Until the advent of the stacked-die assembly, notwithstanding the development of limited multi-layer circuitry, the only ways to increase the complexity of a circuit were to increase the area of semiconductor used or to shrink feature size.
Stacked die technology has taken semiconductor fabrication into the third dimension, allowing a potentially large number of stacked dice to put very complex devices into small appliance footprints. The additional advantage of thin wafer technology combines to put very complex circuitry in the same footprint as a single die.
Stacking dice, though, brings new challenges. Stacking requires that a daughter die be attached to a mother die, typically by an array of solder bumps, and requires that the mother die have contactable points on both top and bottom surfaces of the chip. A daughter die typically has fewer total connection points to its circuitry than does the mother die, resulting in a smaller array of contact pads and solder bumps than the mother die. Often, this means that the connection between mother and daughter, though electrically sound, is insufficiently robust mechanically. This complicates the handling and processing of the mother/daughter assembly during packaging and other processing.